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| author | Sven Schnelle <svens@stackframe.org> | 2012-06-10 19:03:36 +0200 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-06-12 10:01:16 +0200 |
| commit | 0860e723cb40b82a9f7cc2652891499e0161d89e (patch) | |
| tree | e92d02c264411147a88fd2796c2f144da58d2afe /src/arch/x86/coreboot_ram.ld | |
| parent | bb1c42b92037dc3dbbb639a1140dd284e978c595 (diff) | |
udelay: add missing bus frequency
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.
Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/x86/coreboot_ram.ld')
0 files changed, 0 insertions, 0 deletions