diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-04-23 21:08:44 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-04-28 16:46:17 +0000 |
| commit | ef0cb90ae3a5849f17366338ec5f9f77c1fd3850 (patch) | |
| tree | 8cb6be4c4d8cf5f68a836fa76e849ab682a52c23 /src/arch/x86/bootblock_crt0.S | |
| parent | 5b574e1c859a095ecdf2728a1a6db2d854bbb668 (diff) | |
mb/google/deltaur: Disable POWER_OFF_ON_CR50_UPDATE
This is missing configuration of Wiloc projects.
Following Wilco projects configuration. CB:32436
The power architecture on this platform is different than most of our
other x86 devices and needs some special handling to ensure it powers
up again after an EC reset.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/bootblock_crt0.S')
0 files changed, 0 insertions, 0 deletions