diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2018-06-26 12:21:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-12 11:53:18 +0000 |
| commit | 6e3cc8855b9364f0097187936d19ec201a2b20c8 (patch) | |
| tree | 42ee25250dc82c2fab65298a0b5d9eab05df6dd0 /src/arch/riscv | |
| parent | a4fc7bef7ffab0ed5f2bcd2d9b439dc4e49bd016 (diff) | |
soc/intel/skylake: add a space in printing ME FPF status
This is cosmetic change
Before:
ME: Power Management Event : Clean global reset
ME: Progress Phase State : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation : NO
ME: FPF status : fused
After:
ME: Power Management Event : Clean Moff->Mx wake
ME: Progress Phase State : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation : NO
ME: FPF status : fused
Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions