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| author | Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> | 2023-05-22 18:52:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-24 18:28:03 +0000 |
| commit | 3b82131c2822be01feae46e77d51f32b286f04fe (patch) | |
| tree | c448e2dd357a5d750d2cf5fb8af87cebf095f465 /src/arch/riscv/trap_util.S | |
| parent | 3afa59310308ed1f57ef68c725e01e62fe8ad1ea (diff) | |
mb/google/Screebo: Enable AUX DC biasing on C0
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
0 files changed, 0 insertions, 0 deletions