summaryrefslogtreecommitdiff
path: root/src/arch/riscv/prologue.inc
diff options
context:
space:
mode:
authorRichard Spiegel <richard.spiegel@silverbackltd.com>2017-11-09 16:04:35 -0700
committerAaron Durbin <adurbin@chromium.org>2017-11-10 18:22:53 +0000
commit67c2a7b487bfaea90303faa5e8ef9e33c3000f1c (patch)
tree7a3fbda67b43bbcc64a27c6ba2b94745a14f3cd4 /src/arch/riscv/prologue.inc
parent185988234d05e99188e3022056792b73313ea5a6 (diff)
soc/amd/common: Add DRAM clear option to northbridge.c
AmdInitPost() can be instructed to clear DRAM after a reset or to preserve it. Use SetMemParams() to tell AGESA which action to take. Note that any overrides from OemPostParams (OemCustomize.c) are not affected by this change. Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/prologue.inc')
0 files changed, 0 insertions, 0 deletions