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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-09-12 10:37:17 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-16 12:07:06 +0000 |
| commit | 90a439384b3c145be59c25b693b95847e04cb48a (patch) | |
| tree | 2a6af35d28e0656b70bfe34b35098533480db60d /src/arch/riscv/pmp.c | |
| parent | 6580674b349191d097f8ebd4cc82abcd4f13fbc5 (diff) | |
soc/intel/common: Update comment on HFSTS1.spi_protection_mode
The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.
For information on EOM status, please refer secton# 3.6.1 in doc#
612229.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/arch/riscv/pmp.c')
0 files changed, 0 insertions, 0 deletions