RISCV: Clean up the common architectural code

This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
entering main() with no supporting assembly code for startup. The Harvey port
is not complete so it just panics but ... it gets started.

We provide a standard payload function that takes a pointer argument
and makes the jump from machine to supervisor mode;
the days of kernels running in machine mode are over.

We do some small tweaks to the virtual memory code. We temporarily
disable two functions that won't work on some targets as register
numbers changed between 1.7 and 1.9. Once lowrisc catches up
we'll reenable them.

We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
memory setup code.

We now use the _stack and _estack from memlayout so we know where things are.
As time goes on maybe we can kill all the magic numbers.

Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17058
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S
new file mode 100644
index 0000000000..3261a80c2b
--- /dev/null
+++ b/src/arch/riscv/payload.S
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+	.global riscvpayload
+riscvpayload:
+	/* Jump to a0 in S-mode */
+	mv t0,a0
+	csrw mepc, t0
+	csrr t0, mstatus
+	li t1, ~(3<<11)
+	and t0, t0, t1
+	li t2,  (1<<11)
+	or t0, t0, t2
+	csrw mstatus, t0
+
+	// We're still in toolchain no mans land.
+	.word 0x30200073
+	//mret