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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-07-29 19:03:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-01 20:27:32 +0000 |
| commit | 7e75d1ad2615d6096f84b15e20508d60d393868d (patch) | |
| tree | 64e6016edf4f374328a043127dbb61ba8aa82317 /src/arch/riscv/misc.c | |
| parent | 17968caa94aa345affcc14e6f6db2605d31535e3 (diff) | |
soc/amd/common/smi_util: add PSP SMI helper functions
The PSP can send SMIs to the x86 side of the system. Add helper
functions to configure and to reset the PSP SMI generation. Since
Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP
define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific
smi.h to bring it in line with the newer SoCs.
This patch is split out from CB:65523.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/misc.c')
0 files changed, 0 insertions, 0 deletions