diff options
| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2022-06-20 18:00:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-23 12:18:50 +0000 |
| commit | efe749f380f2e2a398ad05f6dc0076957273817e (patch) | |
| tree | 139240741bdf1b193dbab7e875534efdf7e0ad10 /src/arch/riscv/include | |
| parent | d234b07244f59609c636740eb249e20b225470e9 (diff) | |
mb/google/nissa/var/xivu: Generate RAM ID and SPD file
Add the support RAM parts for Xivu.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576117
BRANCH=None
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/include')
0 files changed, 0 insertions, 0 deletions