diff options
| author | Philipp Hug <philipp@hug.cx> | 2018-09-13 18:11:56 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-14 09:28:06 +0000 |
| commit | 199b75f58a0ffc2ad0871eb4853ca425c78b4893 (patch) | |
| tree | fdd1d98ffa45c1e02372f5528f414008de498911 /src/arch/riscv/include | |
| parent | 31dbfbc405ba7b26cacd2cfcaeff95e52d60ad99 (diff) | |
arch/riscv: provide a monotonic timer
The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.
Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.
Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/include')
| -rw-r--r-- | src/arch/riscv/include/arch/io.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/riscv/include/arch/io.h b/src/arch/riscv/include/arch/io.h index 5f66a239b4..6fd0cac88e 100644 --- a/src/arch/riscv/include/arch/io.h +++ b/src/arch/riscv/include/arch/io.h @@ -33,6 +33,11 @@ static __always_inline uint32_t read32(const volatile void *addr) return *((volatile uint32_t *)(addr)); } +static __always_inline uint64_t read64(const volatile void *addr) +{ + return *((volatile uint64_t *)(addr)); +} + static __always_inline void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; @@ -48,4 +53,9 @@ static __always_inline void write32(volatile void *addr, uint32_t value) *((volatile uint32_t *)(addr)) = value; } +static __always_inline void write64(volatile void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = value; +} + #endif |