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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-06 10:35:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-07 16:47:01 +0000 |
| commit | 0d0ebb6be9f0c87ea557c78c58dc8e06afe51183 (patch) | |
| tree | fddfc94b20ef71b47efa72f39ec014ca5b36167b /src/arch/power8 | |
| parent | a29d4d290840002cf07e5bef28fcfdb9b445f5c7 (diff) | |
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/power8')
0 files changed, 0 insertions, 0 deletions