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| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-10-24 13:01:28 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-27 17:01:46 +0200 |
| commit | d5353e36483daef462fd37e47aa4c0524f868ace (patch) | |
| tree | 7618ffa50ae2700fc8ec630b0fab2674f9b7d66d /src/arch/mips | |
| parent | 6ea1500e48aa86ca0ae5da2227a65a3e5b5420db (diff) | |
driver/intel/fsp2_0: Reset on invalid stage cache.
Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is
invalid during S3 resume.
Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/mips')
0 files changed, 0 insertions, 0 deletions