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| author | Fabian Kunkel <fabi@adv.bruhnspace.com> | 2016-07-26 22:46:23 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 20:00:14 +0200 |
| commit | 8cab72e1d857d430b5c9c4b748f4b46a84374168 (patch) | |
| tree | 679cf22a626736f9fcb9be929e15f3d51748441c /src/arch/mips/boot.c | |
| parent | 1f9c07fcd735e2e55104d1b3a2672298a460d5fb (diff) | |
mainboard/bap/ode_e20XX: Add different DDR3 clk settings
This patch adds two SPD files with different DDR3 clk settings.
The user can choose which setting to use.
Lower clk settings saves power under load.
SoC Model GX-411GA supports only up to DDR3-1066 clk mode.
Both SPD settings were tested with memtest for several hours.
Power saving is around half a watt under heavy memory load.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0
Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/arch/mips/boot.c')
0 files changed, 0 insertions, 0 deletions