- Update abuild.sh so it will rebuild successfull builds

- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 240 insertions, 217 deletions

diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb
index 82adea0e0c..6de19b65be 100644
--- a/src/arch/i386/lib/Config.lb
+++ b/src/arch/i386/lib/Config.lb
@@ -7,4 +7,7 @@
 object c_start.S
 object cpu.c
 object pci_ops.c
+object pci_ops_conf1.c
+object pci_ops_conf2.c
+object pci_ops_auto.c
 object exception.c
diff --git a/src/arch/i386/lib/pci_ops.c b/src/arch/i386/lib/pci_ops.c
index 9a8616a90a..ded7fd20a4 100644
--- a/src/arch/i386/lib/pci_ops.c
+++ b/src/arch/i386/lib/pci_ops.c
@@ -5,218 +5,12 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
-static const struct pci_ops *conf;
-struct pci_ops {
-	uint8_t (*read8)   (uint8_t bus, int devfn, int where);
-	uint16_t (*read16) (uint8_t bus, int devfn, int where);
-	uint32_t (*read32) (uint8_t bus, int devfn, int where);
-	void (*write8)  (uint8_t bus, int devfn, int where, uint8_t val);
-	void (*write16) (uint8_t bus, int devfn, int where, uint16_t val);
-	void (*write32) (uint8_t bus, int devfn, int where, uint32_t val);
-};
+const struct pci_ops *conf = 0;
 
 /*
  * Direct access to PCI hardware...
  */
 
-
-/*
- * Functions for accessing PCI configuration space with type 1 accesses
- */
-
-#define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
-
-static uint8_t pci_conf1_read_config8(unsigned char bus, int devfn, int where)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	return inb(0xCFC + (where & 3));
-}
-
-static uint16_t pci_conf1_read_config16(unsigned char bus, int devfn, int where)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	return inw(0xCFC + (where & 2));
-}
-
-static uint32_t pci_conf1_read_config32(unsigned char bus, int devfn, int where)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	return inl(0xCFC);
-}
-
-static void  pci_conf1_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	outb(value, 0xCFC + (where & 3));
-}
-
-static void pci_conf1_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	outw(value, 0xCFC + (where & 2));
-}
-
-static void pci_conf1_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
-{
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
-	outl(value, 0xCFC);
-}
-
-#undef CONFIG_CMD
-
-static const struct pci_ops pci_direct_conf1 =
-{
-	.read8  = pci_conf1_read_config8,
-	.read16 = pci_conf1_read_config16,
-	.read32 = pci_conf1_read_config32,
-	.write8  = pci_conf1_write_config8,
-	.write16 = pci_conf1_write_config16,
-	.write32 = pci_conf1_write_config32,
-};
-
-/*
- * Functions for accessing PCI configuration space with type 2 accesses
- */
-
-#define IOADDR(devfn, where)	((0xC000 | ((devfn & 0x78) << 5)) + where)
-#define FUNC(devfn)		(((devfn & 7) << 1) | 0xf0)
-#define SET(bus,devfn)		outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
-
-static uint8_t pci_conf2_read_config8(unsigned char bus, int devfn, int where)
-{
-	uint8_t value;
-	SET(bus, devfn);
-	value = inb(IOADDR(devfn, where));
-	outb(0, 0xCF8);
-	return value;
-}
-
-static uint16_t pci_conf2_read_config16(unsigned char bus, int devfn, int where)
-{
-	uint16_t value;
-	SET(bus, devfn);
-	value = inw(IOADDR(devfn, where));
-	outb(0, 0xCF8);
-	return value;
-}
-
-static uint32_t pci_conf2_read_config32(unsigned char bus, int devfn, int where)
-{
-	uint32_t value;
-	SET(bus, devfn);
-	value = inl(IOADDR(devfn, where));
-	outb(0, 0xCF8);
-	return value;
-}
-
-static void pci_conf2_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
-{
-	SET(bus, devfn);
-	outb(value, IOADDR(devfn, where));
-	outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
-{
-	SET(bus, devfn);
-	outw(value, IOADDR(devfn, where));
-	outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
-{
-	SET(bus, devfn);
-	outl(value, IOADDR(devfn, where));
-	outb(0, 0xCF8);
-}
-
-#undef SET
-#undef IOADDR
-#undef FUNC
-
-static const struct pci_ops pci_direct_conf2 =
-{
-	.read8  = pci_conf2_read_config8,
-	.read16 = pci_conf2_read_config16,
-	.read32 = pci_conf2_read_config32,
-	.write8  = pci_conf2_write_config8,
-	.write16 = pci_conf2_write_config16,
-	.write32 = pci_conf2_write_config32,
-};
-
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int pci_sanity_check(const struct pci_ops *o)
-{
-	uint16_t class, vendor;
-	uint8_t bus;
-	int devfn;
-#define PCI_CLASS_BRIDGE_HOST		0x0600
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_VENDOR_ID_COMPAQ		0x0e11
-#define PCI_VENDOR_ID_INTEL		0x8086
-#define PCI_VENDOR_ID_MOTOROLA		0x1057
-
-	for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
-		class = o->read16(bus, devfn, PCI_CLASS_DEVICE);
-		vendor = o->read16(bus, devfn, PCI_VENDOR_ID);
-		if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
-			((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
-				(vendor == PCI_VENDOR_ID_MOTOROLA))) { 
-			return 1;
-		}
-	}
-	printk_err("PCI: Sanity check failed\n");
-	return 0;
-}
-
-static const struct pci_ops *pci_check_direct(void)
-{
-	unsigned int tmp;
-
-	/*
-	 * Check if configuration type 1 works.
-	 */
-	{
-		outb(0x01, 0xCFB);
-		tmp = inl(0xCF8);
-		outl(0x80000000, 0xCF8);
-		if (inl(0xCF8) == 0x80000000 &&
-		    pci_sanity_check(&pci_direct_conf1)) {
-			outl(tmp, 0xCF8);
-			printk_debug("PCI: Using configuration type 1\n");
-			return &pci_direct_conf1;
-		}
-		outl(tmp, 0xCF8);
-	}
-
-	/*
-	 * Check if configuration type 2 works.
-	 */
-	{
-		outb(0x00, 0xCFB);
-		outb(0x00, 0xCF8);
-		outb(0x00, 0xCFA);
-		if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
-		    pci_sanity_check(&pci_direct_conf2)) {
-			printk_debug("PCI: Using configuration type 2\n");
-			return &pci_direct_conf2;
-		}
-	}
-
-	printk_debug("pci_check_direct failed\n");
-    
-	return 0;
-}
-
 uint8_t pci_read_config8(device_t dev, unsigned where)
 {
 	uint8_t value;
@@ -264,13 +58,3 @@ void pci_write_config32(device_t dev, unsigned where, uint32_t val)
 		     dev->bus->secondary, dev->path.u.pci.devfn, where, val);
 	conf->write32(dev->bus->secondary, dev->path.u.pci.devfn, where, val);
 }
-
-/** Set the method to be used for PCI, type I or type II
- */
-void pci_set_method(void)
-{
-	conf = &pci_direct_conf1;
-	conf = pci_check_direct();
-}
-
-
diff --git a/src/arch/i386/lib/pci_ops_auto.c b/src/arch/i386/lib/pci_ops_auto.c
new file mode 100644
index 0000000000..5c45720888
--- /dev/null
+++ b/src/arch/i386/lib/pci_ops_auto.c
@@ -0,0 +1,92 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pciconf.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+/*
+ * Before we decide to use direct hardware access mechanisms, we try to do some
+ * trivial checks to ensure it at least _seems_ to be working -- we just test
+ * whether bus 00 contains a host bridge (this is similar to checking
+ * techniques used in XFree86, but ours should be more reliable since we
+ * attempt to make use of direct access hints provided by the PCI BIOS).
+ *
+ * This should be close to trivial, but it isn't, because there are buggy
+ * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
+ */
+static int pci_sanity_check(const struct pci_ops *o)
+{
+	uint16_t class, vendor;
+	uint8_t bus;
+	int devfn;
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+
+	for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
+		class = o->read16(bus, devfn, PCI_CLASS_DEVICE);
+		vendor = o->read16(bus, devfn, PCI_VENDOR_ID);
+		if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
+			((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
+				(vendor == PCI_VENDOR_ID_MOTOROLA))) { 
+			return 1;
+		}
+	}
+	printk_err("PCI: Sanity check failed\n");
+	return 0;
+}
+
+static void pci_check_direct(void)
+{
+	unsigned int tmp;
+
+	/*
+	 * Check if configuration type 1 works.
+	 */
+	{
+		outb(0x01, 0xCFB);
+		tmp = inl(0xCF8);
+		outl(0x80000000, 0xCF8);
+		if (inl(0xCF8) == 0x80000000) {
+			pci_set_method_conf1();
+			if (pci_sanity_check(conf)) {
+				outl(tmp, 0xCF8);
+				printk_debug("PCI: Using configuration type 1\n");
+				return;
+			}
+		}
+		outl(tmp, 0xCF8);
+	}
+
+	/*
+	 * Check if configuration type 2 works.
+	 */
+	{
+		outb(0x00, 0xCFB);
+		outb(0x00, 0xCF8);
+		outb(0x00, 0xCFA);
+		if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) {
+			pci_set_method_conf2();
+			if (pci_sanity_check(conf)) {
+				printk_debug("PCI: Using configuration type 2\n");
+			}
+		}
+	}
+
+	printk_debug("pci_check_direct failed\n");
+	conf = 0;
+    
+	return;
+}
+
+/** Set the method to be used for PCI, type I or type II
+ */
+void pci_set_method(void)
+{
+	printk_info("Finding PCI configuration type.\n");
+	pci_check_direct();
+	post_code(0x5f);
+}
diff --git a/src/arch/i386/lib/pci_ops_conf1.c b/src/arch/i386/lib/pci_ops_conf1.c
new file mode 100644
index 0000000000..1324add74a
--- /dev/null
+++ b/src/arch/i386/lib/pci_ops_conf1.c
@@ -0,0 +1,64 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pciconf.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+/*
+ * Functions for accessing PCI configuration space with type 1 accesses
+ */
+
+#define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
+
+static uint8_t pci_conf1_read_config8(unsigned char bus, int devfn, int where)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	return inb(0xCFC + (where & 3));
+}
+
+static uint16_t pci_conf1_read_config16(unsigned char bus, int devfn, int where)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	return inw(0xCFC + (where & 2));
+}
+
+static uint32_t pci_conf1_read_config32(unsigned char bus, int devfn, int where)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	return inl(0xCFC);
+}
+
+static void  pci_conf1_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outb(value, 0xCFC + (where & 3));
+}
+
+static void pci_conf1_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outw(value, 0xCFC + (where & 2));
+}
+
+static void pci_conf1_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
+{
+	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(value, 0xCFC);
+}
+
+#undef CONFIG_CMD
+
+static const struct pci_ops pci_direct_conf1 =
+{
+	.read8  = pci_conf1_read_config8,
+	.read16 = pci_conf1_read_config16,
+	.read32 = pci_conf1_read_config32,
+	.write8  = pci_conf1_write_config8,
+	.write16 = pci_conf1_write_config16,
+	.write32 = pci_conf1_write_config32,
+};
+
+void pci_set_method_conf1(void)
+{
+	conf = &pci_direct_conf1;
+}
diff --git a/src/arch/i386/lib/pci_ops_conf2.c b/src/arch/i386/lib/pci_ops_conf2.c
new file mode 100644
index 0000000000..9fa03f18a8
--- /dev/null
+++ b/src/arch/i386/lib/pci_ops_conf2.c
@@ -0,0 +1,80 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pciconf.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+/*
+ * Functions for accessing PCI configuration space with type 2 accesses
+ */
+
+#define IOADDR(devfn, where)	((0xC000 | ((devfn & 0x78) << 5)) + where)
+#define FUNC(devfn)		(((devfn & 7) << 1) | 0xf0)
+#define SET(bus,devfn)		outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
+
+static uint8_t pci_conf2_read_config8(unsigned char bus, int devfn, int where)
+{
+	uint8_t value;
+	SET(bus, devfn);
+	value = inb(IOADDR(devfn, where));
+	outb(0, 0xCF8);
+	return value;
+}
+
+static uint16_t pci_conf2_read_config16(unsigned char bus, int devfn, int where)
+{
+	uint16_t value;
+	SET(bus, devfn);
+	value = inw(IOADDR(devfn, where));
+	outb(0, 0xCF8);
+	return value;
+}
+
+static uint32_t pci_conf2_read_config32(unsigned char bus, int devfn, int where)
+{
+	uint32_t value;
+	SET(bus, devfn);
+	value = inl(IOADDR(devfn, where));
+	outb(0, 0xCF8);
+	return value;
+}
+
+static void pci_conf2_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
+{
+	SET(bus, devfn);
+	outb(value, IOADDR(devfn, where));
+	outb(0, 0xCF8);
+}
+
+static void pci_conf2_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
+{
+	SET(bus, devfn);
+	outw(value, IOADDR(devfn, where));
+	outb(0, 0xCF8);
+}
+
+static void pci_conf2_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
+{
+	SET(bus, devfn);
+	outl(value, IOADDR(devfn, where));
+	outb(0, 0xCF8);
+}
+
+#undef SET
+#undef IOADDR
+#undef FUNC
+
+static const struct pci_ops pci_direct_conf2 =
+{
+	.read8  = pci_conf2_read_config8,
+	.read16 = pci_conf2_read_config16,
+	.read32 = pci_conf2_read_config32,
+	.write8  = pci_conf2_write_config8,
+	.write16 = pci_conf2_write_config16,
+	.write32 = pci_conf2_write_config32,
+};
+
+void pci_set_method_conf2(void)
+{
+	conf = &pci_direct_conf2;
+}