diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-30 21:52:05 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-30 21:52:05 +0000 |
commit | cca626817dc88bfaec8b6ebf787f5f57006fe0cb (patch) | |
tree | a69b43a9ae39de47b4cd6da7fe81a8e3488b03fe /src/arch/i386/coreboot_apc.ld | |
parent | c269d237f93d7867c7f4cad9a4d619b56f4a3d81 (diff) |
get coreboot_ap memory training in cache mechanism in place. Didn't work since
Kconfig (needs more patches to ap_romstage.c but this is a first step)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/i386/coreboot_apc.ld')
-rw-r--r-- | src/arch/i386/coreboot_apc.ld | 100 |
1 files changed, 0 insertions, 100 deletions
diff --git a/src/arch/i386/coreboot_apc.ld b/src/arch/i386/coreboot_apc.ld deleted file mode 100644 index d7820aafe1..0000000000 --- a/src/arch/i386/coreboot_apc.ld +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Memory map: - * - * CONFIG_DCACHE_RAM_BASE - * : data segment - * : bss segment - * : heap - * : stack - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - * 2006.05 yhlu tailed it to use it for AP code in cache - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ -INCLUDE ldoptions - -ENTRY(_start) - -SECTIONS -{ - . = CONFIG_DCACHE_RAM_BASE; - /* - * First we place the code and read only data (typically const declared). - * This get placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - .rodata : { - _rodata = .; - . = ALIGN(4); - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - _erodata = .; - } - /* - * After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - /* - * bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - . = ALIGN(0x1000); - _stack = .; - .stack . : { - . = 0x4000; - } - _estack = .; - _heap = .; - .heap . : { - . = ALIGN(4); - } - _eheap = .; - /* The ram segment - * This is all address of the memory resident copy of coreboot. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} |