diff options
| author | Julius Werner <jwerner@chromium.org> | 2013-09-18 14:39:50 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-08-10 22:18:50 +0200 |
| commit | 985ff36bee24d1e5a8bd698409a0a05e15528c01 (patch) | |
| tree | 029ed9a091d2c79b345e159765c153bf4000646e /src/arch/armv7/bootblock.inc | |
| parent | 802ad521804b8a9f473780fdff4058dd3f8520c3 (diff) | |
armv7: Support stack dump after exceptions
This patch enhances the armv7 exception handlers in Coreboot and
libpayload to show the correct SP and LR registers from the aborted
context, and also dump a part of the current stack. Since we cannot
access the banked registers of SVC mode from a different exception mode,
it changes Coreboot (and its payloads) to run in System mode instead. As
both modes can execute all privileged instructions, this should not have
any noticeable effect on firmware operation (please correct me if I'm
wrong!).
Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170045
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6538
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7/bootblock.inc')
| -rw-r--r-- | src/arch/armv7/bootblock.inc | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c45259db6d..b28a787839 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -43,15 +43,12 @@ _cbfs_master_header: reset: /* - * Set the cpu to SVC32 mode and unmask aborts. Aborts might happen - * before logging is turned on and may crash the machine, but at least - * the problem will show up near the code that causes it. + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0xd3 - bic r0, r0, #0x100 - msr cpsr_cxsf,r0 + msr cpsr_cxf, #0xdf /* * From Cortex-A Series Programmer's Guide: |