armv7: update coreboot tables for armv7

This is a first-pass attempt at cleaning up the coreboot tables
for ARM. The most noticable difference is that there is no longer
both a high and a low table.

Change-Id: I5ba87ad57bf9a697b733511182c0326825071617
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2 files changed, 58 insertions, 83 deletions

diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c
index b2d88aa776..ed105a4fc9 100644
--- a/src/arch/armv7/boot/coreboot_table.c
+++ b/src/arch/armv7/boot/coreboot_table.c
@@ -559,11 +559,13 @@ struct lb_memory *get_lb_mem(void)
 	return mem_ranges;
 }
 
+#if 0
 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res)
 {
 	struct lb_memory *mem = gp;
 	new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size);
 }
+#endif
 
 static struct lb_memory *build_lb_mem(struct lb_header *head)
 {
@@ -573,11 +575,15 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
 	mem = lb_memory(head);
 	mem_ranges = mem;
 
+	/* FIXME: implement this */
+#if 0
 	/* Build the raw table of memory */
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		build_lb_mem_range, mem);
-	lb_cleanup_memory_ranges(mem);
+#endif
+	/* FIXME: things die in cleanup_memory_ranges(), skip for now */
+//	lb_cleanup_memory_ranges(mem);
 	return mem;
 }
 
@@ -596,47 +602,27 @@ static void add_lb_reserved(struct lb_memory *mem)
 }
 
 unsigned long write_coreboot_table(
-	unsigned long low_table_start, unsigned long low_table_end,
-	unsigned long rom_table_start, unsigned long rom_table_end)
+	unsigned long table_start, unsigned long table_end)
 {
 	struct lb_header *head;
 	struct lb_memory *mem;
+	unsigned long fini;
 
-#if CONFIG_WRITE_HIGH_TABLES
-	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
-			low_table_end);
-	head = lb_table_init(low_table_end);
-	lb_forward(head, (struct lb_header*)rom_table_end);
-
-	low_table_end = (unsigned long) lb_table_fini(head, 0);
-	printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end);
-	printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n",
-			rom_table_end);
-
-	head = lb_table_init(rom_table_end);
-	rom_table_end = (unsigned long)head;
-	printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
-#else
-	if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */
-		/* We need to put lbtable on  to [0xf0000,0x100000) */
-		head = lb_table_init(rom_table_end);
-		rom_table_end = (unsigned long)head;
-	} else {
-		head = lb_table_init(low_table_end);
-		low_table_end = (unsigned long)head;
-	}
-#endif
+	printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx\n",
+			   table_start, table_end);
+	head = lb_table_init(table_start);
+
+	printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
+			table_end);
+	lb_forward(head, (struct lb_header*)table_end);
 
-	printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end);
-	low_table_end += 0xfff; // 4K aligned
-	low_table_end &= ~0xfff;
-	printk(BIOS_DEBUG, "0x%08lx \n", low_table_end);
+	table_end = (unsigned long) head + head->table_bytes;
 
-	/* The Linux kernel assumes this region is reserved */
-	printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end);
-	rom_table_end += 0xffff; // 64K align
-	rom_table_end &= ~0xffff;
-	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
+	/* FIXME(dhendrix): do we need this? */
+	printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end);
+	table_end += 0xfff; // 4K aligned
+	table_end &= ~0xfff;
+	printk(BIOS_DEBUG, "0x%08lx \n", table_end);
 
 #if CONFIG_USE_OPTION_TABLE
 	{
@@ -655,21 +641,29 @@ unsigned long write_coreboot_table(
 	}
 #endif
 	/* Record where RAM is located */
+	/* FIXME(dhendrix): add global resources */
+	printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head);
 	mem = build_lb_mem(head);
+	/* FIXME: we seem to get a bogus return value */
+	printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem);
+	if ((unsigned long)mem < CONFIG_RAMBASE) {
+		printk(BIOS_DEBUG, "%s: mem < CONFIG_RAMBASE\n" , __func__);
+		while (1);
+	}
 
 	/* Record the mptable and the the lb_table (This will be adjusted later) */
 	lb_add_memory_range(mem, LB_MEM_TABLE,
-		low_table_start, low_table_end - low_table_start);
+		table_start, table_end - table_start);
 
 	/* Record the pirq table, acpi tables, and maybe the mptable */
 	lb_add_memory_range(mem, LB_MEM_TABLE,
-		rom_table_start, rom_table_end-rom_table_start);
+		table_start, table_end - table_start);
 
 #if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
-		high_tables_base, high_tables_size);
+			table_start, table_end - table_start);
 #endif
 
 	/* Add reserved regions */
@@ -679,11 +673,12 @@ unsigned long write_coreboot_table(
 
 	/* Note:
 	 * I assume that there is always memory at immediately after
-	 * the low_table_end.  This means that after I setup the coreboot table.
+	 * the table_end.  This means that after I setup the coreboot table.
 	 * I can trivially fixup the reserved memory ranges to hold the correct
 	 * size of the coreboot table.
 	 */
 
+	/* FIXME(dhendrix): Most of these do nothing at the moment */
 	/* Record our motherboard */
 	lb_mainboard(head);
 	/* Record the serial port, if present */
@@ -695,6 +690,7 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if 0
 #if CONFIG_CHROMEOS
 	/* Record our GPIO settings (ChromeOS specific) */
 	lb_gpios(head);
@@ -705,9 +701,12 @@ unsigned long write_coreboot_table(
 	/* pass along VBNV offsets in CMOS */
 	lb_vbnv(head);
 #endif
+#endif
 	add_cbmem_pointers(head);
 
 	/* Remember where my valid memory ranges are */
-	return lb_table_fini(head, 1);
+	fini =  lb_table_fini(head, 1);
+	printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini);
+	return fini;
 
 }
diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c
index 07c56354c8..813eaeab5d 100644
--- a/src/arch/armv7/boot/tables.c
+++ b/src/arch/armv7/boot/tables.c
@@ -28,6 +28,10 @@
 #include <cbmem.h>
 #include <lib.h>
 
+/*
+ * TODO: "High" tables are a convention used on x86. Maybe we can
+ * clean up that naming at some point.
+ */
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
 
@@ -37,58 +41,30 @@ void cbmem_arch_init(void)
 
 struct lb_memory *write_tables(void)
 {
-	unsigned long low_table_start, low_table_end;
-	unsigned long rom_table_start, rom_table_end;
-
-	/* Even if high tables are configured, some tables are copied both to
-	 * the low and the high area, so payloads and OSes don't need to know
-	 * about the high tables.
-	 */
-	unsigned long high_table_pointer;
+	unsigned long table_pointer;
 
 	if (!high_tables_base) {
-		printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
+		printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n");
 		// Are there any boards without?
 		// Stepan thinks we should die() here!
 	}
 
-	printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
-
-	rom_table_start = 0xf0000;
-	rom_table_end =   0xf0000;
-
-	/* Start low addr at 0x500, so we don't run into conflicts with the BDA
-	 * in case our data structures grow beyound 0x400. Only multiboot, GDT
-	 * and the coreboot table use low_tables.
-	 */
-	low_table_start = 0;
-	low_table_end = 0x500;
+	printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base);
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
 	post_code(0x9d);
 
-	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
-
-	if (high_table_pointer) {
-		unsigned long new_high_table_pointer;
-
-		/* Also put a forwarder entry into 0-4K */
-		new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
-				high_tables_base, high_table_pointer);
-
-		if (new_high_table_pointer > (high_table_pointer +
-					MAX_COREBOOT_TABLE_SIZE))
+	table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+						MAX_COREBOOT_TABLE_SIZE);
+	if (table_pointer) {
+		unsigned long new_table_pointer;
+		new_table_pointer = write_coreboot_table(table_pointer,
+							high_tables_size);
+		if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
 			printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n",
-				   __func__, new_high_table_pointer -
-				   high_table_pointer);
-
-                printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
-				new_high_table_pointer - high_table_pointer);
-	} else {
-		/* The coreboot table must be in 0-4K or 960K-1M */
-		rom_table_end = write_coreboot_table(
-				     low_table_start, low_table_end,
-				     rom_table_start, rom_table_end);
+				   __func__, new_table_pointer - table_pointer);
+		}
+		printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+			new_table_pointer - table_pointer);
 	}
 
 	post_code(0x9e);