coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 9 insertions, 9 deletions

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 80023c4418..14f5f7ade9 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -37,7 +37,7 @@
 
 #include <arch/cache.h>
 
-#if IS_ENABLED(CONFIG_ARM_LPAE)
+#if CONFIG(ARM_LPAE)
 /* See B3.6.2 of ARMv7 Architecture Reference Manual */
 /* TODO: Utilize the contiguous hint flag */
 #define ATTR_BLOCK (\
@@ -170,7 +170,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry)
 	/* Initialize the new subtable with entries of the same attributes
 	 * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */
 	pte_t attr = *pgd_entry & ~(BLOCK_MASK);
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 	if (attr & ATTR_BLOCK)
 		attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE;
@@ -208,7 +208,7 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 
 	/* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */
 	pte_t attr = attrs[policy].value;
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 
 	/* Mask away high address bits that are handled by upper level table. */
diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h
index f7837b68c8..4ba2bf8cf2 100644
--- a/src/arch/arm/include/arch/memlayout.h
+++ b/src/arch/arm/include/arch/memlayout.h
@@ -18,16 +18,16 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M)
+#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M)
 
 #define TTB(addr, size) \
 	REGION(ttb, addr, size, 16K) \
-	_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
+	_ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \
 		"TTB must be 16K (+ 32 for LPAE)!");
 
 #define TTB_SUBTABLES(addr, size) \
-	REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \
-	_ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \
+	REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \
+	_ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \
 		"TTB subtable region must be evenly divisible by table size!");
 
 /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 9a8021761e..b2b6a33333 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -134,7 +134,7 @@ static inline void write_mair0(uint32_t val)
 /* write translation table base register 0 (TTBR0) */
 static inline void write_ttbr0(uint32_t val)
 {
-	if (IS_ENABLED(CONFIG_ARM_LPAE))
+	if (CONFIG(ARM_LPAE))
 		asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
 			[val] "r" (val), [zero] "r" (0));
 	else
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
index 7f8e2a03f0..682715f8c1 100644
--- a/src/arch/arm/tables.c
+++ b/src/arch/arm/tables.c
@@ -32,7 +32,7 @@ void bootmem_arch_add_ranges(void)
 	bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
 			  BM_MEM_RAMSTAGE);
 
-	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+	if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
 			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);