diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-07-10 12:40:30 -0500 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-04 20:00:18 +0100 |
| commit | 0df877a65ac6563f1e46eea9e15e34a366d7105f (patch) | |
| tree | 132bea64b5c92123ea72260eedb0da2a166b1380 /src/arch/arm64/bootblock.ld | |
| parent | 6ba1b628eeabef60ea6b0abeea0d2825ddf99dfe (diff) | |
arm64: use one stage_entry for all stages
Ramstage needs an assembly entry point for setting up
the initial state of the CPU. Therefore, a function is
provided, arm64_el3_startup(), that bootstraps the state
of the processor, initializes the stack pointer, and
branches to a defined entry symbol. To make this work
without adding too much preprocessor macro conditions
provide _stack and _estack for all the stages.
Currently the entry point after initialization is 'main',
however it can be changed/extended to do more work such
as seeding the stack contents with tombstones, etc.
It should be noted that romstage and bootblock weren't
tested. Only ramstage is known to work.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Brought up 64-bit ramstage on rush.
Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207262
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949
Reviewed-on: http://review.coreboot.org/8585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/arch/arm64/bootblock.ld')
| -rw-r--r-- | src/arch/arm64/bootblock.ld | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index 907d009b7d..775111bfd0 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -28,14 +28,14 @@ PHDRS to_load PT_LOAD; } -ENTRY(_start) +ENTRY(stage_entry) TARGET(binary) SECTIONS { . = CONFIG_BOOTBLOCK_BASE; .bootblock . : { - *(.text._start); + *(.text.stage_entry); KEEP(*(.id)); *(.text); *(.text.*); @@ -49,6 +49,10 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + /* arm64 chipsets need to define CONFIG_BOOTBLOCK_STACK_(TOP|BOTTOM) */ + _stack = CONFIG_BOOTBLOCK_STACK_BOTTOM; + _estack = CONFIG_BOOTBLOCK_STACK_TOP; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { |