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authorNico Huber <nico.huber@secunet.com>2021-07-26 13:44:19 +0000
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-01-24 07:59:18 +0000
commit792ed6353a80fcebbc74f8a34e37c10eaf6ff62b (patch)
treeb00fee6b2195d4f14f288fb76cbc0945a5c1e8ff /src/arch/arm/div0.c
parent0030349e2deab5f4041745ec8474e03b7e5c329e (diff)
soc/intel/cannonlake: Report correct latencies for C states
The C_STATE_LATENCY_FROM_LAT_REG() macro uses values that we also write into the respective MSRs in configure_c_states(). Match the indices to those used there. Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/arch/arm/div0.c')
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