ACPI: Refactor ChromeOS specific ACPI GNVS

The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.

If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.

If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.

Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.

Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 0 insertions, 12 deletions

diff --git a/src/acpi/nvs.c b/src/acpi/nvs.c
index a7915f2164..12d124f64f 100644
--- a/src/acpi/nvs.c
+++ b/src/acpi/nvs.c
@@ -13,15 +13,3 @@ uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs)
 {
 	return &gnvs->cbmc;
 }
-
-/* Some <soc/nvs.h> have no chromeos entry. */
-void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
-{
-#if CONFIG(BOARD_EMULATION_QEMU_X86_Q35)
-	return NULL;
-#elif CONFIG(MAINBOARD_HAS_CHROMEOS)
-	return &gnvs->chromeos;
-#else
-	return NULL;
-#endif
-}