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author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 16:35:45 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:34:20 +0000 |
commit | df8462c36ad9875a617bee23d3d6281f6990aa53 (patch) | |
tree | 07471e90132d9607b1b3c9df2dcc222e581c30c5 /src/acpi/dsdt_top.asl | |
parent | 560eab7de516f964ed0d1902a811be3be4996d46 (diff) |
soc/intel/skylake/pmutil: Correct soc_smi_sts_array()
The array was copied from Broadwell, which uses a different bit layout
for SMI_STS. Copy the array from Cannonlake instead, because Skylake
uses the same bit layout. This could be deduplicated in the future.
Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/acpi/dsdt_top.asl')
0 files changed, 0 insertions, 0 deletions