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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-04 21:08:17 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-07 20:03:55 +0000
commitb72b5d95286a2290554399e0803d4ba5e7b87f8d (patch)
tree8ea86f16a8fffce3650e887ccdc0f8dae0947c96 /src/Kconfig
parent3a2660e489d44d29b647e8594e8134e6ee8fc03b (diff)
arch/x86: Clean up PIRQ_ROUTE
This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/Kconfig')
-rw-r--r--src/Kconfig15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 919d257c62..778f1694b6 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
-config PIRQ_ROUTE
- bool
- default n
-
config HAVE_SMI_HANDLER
bool
default n
@@ -591,17 +587,6 @@ config HAVE_PIRQ_TABLE
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.
-config MAX_PIRQ_LINKS
- int
- default 4
- help
- This variable specifies the number of PIRQ interrupt links which are
- routable. On most chipsets, this is 4, INTA through INTD. Some
- chipsets offer more than four links, commonly up to INTH. They may
- also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
- table specifies links greater than 4, pirq_route_irqs will not
- function properly, unless this variable is correctly set.
-
config COMMON_FADT
bool
default n