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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-08-23 02:32:58 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-10-04 04:27:29 +0200
commit70c660fd1473b8c6ca7b71276b9552ee2205c99a (patch)
tree51bb9ef72dbe12fa6701005397f2a0c2c06bd688 /src/Kconfig
parent93a8b27cbed8a288ee6a65436ec22ad5a67fdbd0 (diff)
pirq_routing: Allow routing with more than 4 PIRQ links
pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1482 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/Kconfig')
-rw-r--r--src/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 469266dde9..e0062dde6e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1,6 +1,7 @@
##
## This file is part of the coreboot project.
##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
## Copyright (C) 2009-2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
@@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.
+config MAX_PIRQ_LINKS
+ int
+ default 4
+ help
+ This variable specifies the number of PIRQ interrupt links which are
+ routable. On most chipsets, this is 4, INTA through INTD. Some
+ chipsets offer more than four links, commonly up to INTH. They may
+ also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
+ table specifies links greater than 4, pirq_route_irqs will not
+ function properly, unless this variable is correctly set.
+
#These Options are here to avoid "undefined" warnings.
#The actual selection and help texts are in the following menu.