Fix the NVRAM access functions to work correctly for the

upper 128 bytes of NVRAM (if enabled).

For most chipsets this means using I/O ports 0x72/0x73, but at least
on some VIA chipsets (I tested the VIA VT8237R on actual hardware)
these ports won't work and you have to use 0x74/0x75. Thus, make this
a Kconfig option for now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 48 insertions, 6 deletions

diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
index a1343f566b..fbb477ed7f 100644
--- a/payloads/libpayload/Config.in
+++ b/payloads/libpayload/Config.in
@@ -72,6 +72,22 @@ config NVRAM
 	bool "Support for reading/writing NVRAM bytes"
 	default y
 
+config RTC_PORT_EXTENDED_VIA
+	bool "Extended RTC ports are 0x74/0x75"
+	default n
+	help
+	  For recent chipsets with 256 NVRAM bytes, you have to access the
+	  upper 128 bytes (128-255) using two different I/O ports,
+	  usually 0x72/0x73.
+	
+	  On some chipsets this can be a different set of ports, though.
+	  The VIA VT8237R for example only recognizes the ports 0x74/0x75
+	  for accessing the high 128 NVRAM bytes (as seems to be the case for
+	  multiple VIA chipsets).
+	
+	  If you want to read or write CMOS bytes on computers with one of
+	  these chipsets, say 'y' here.
+
 endmenu
 
 menu "Build Options"
diff --git a/payloads/libpayload/curses/Makefile.inc b/payloads/libpayload/curses/Makefile.inc
index 8c6fb784a0..745e38362b 100644
--- a/payloads/libpayload/curses/Makefile.inc
+++ b/payloads/libpayload/curses/Makefile.inc
@@ -27,7 +27,7 @@
 ## SUCH DAMAGE.
 ##
 
-TARGETS-$(CONFIG_TINYCURSES) += curses/keyboard.o 
+TARGETS-$(CONFIG_TINYCURSES) += curses/keyboard.o
 TARGETS-$(CONFIG_TINYCURSES) += curses/tinycurses.o
 TARGETS-$(CONFIG_TINYCURSES) += curses/speaker.o
 TARGETS-$(CONFIG_TINYCURSES) += curses/colors.o
diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c
index 3789c09b3c..9196d80b86 100644
--- a/payloads/libpayload/drivers/nvram.c
+++ b/payloads/libpayload/drivers/nvram.c
@@ -42,7 +42,29 @@
 
 #include <libpayload.h>
 
-#define RTC_PORT 0x70
+
+/**
+ * PCs can have either 64 (very old ones), 128, or 256 bytes of CMOS RAM.
+ *
+ * Usually you access the lower 128 CMOS bytes via I/O port 0x70/0x71.
+ * For more recent chipsets with 256 bytes, you have to access the upper
+ * 128 bytes (128-255) using two different registers, usually 0x72/0x73.
+ *
+ * On some chipsets this can be different, though. The VIA VT8237R for example
+ * only recognizes the ports 0x74/0x75 for accessing the high 128 CMOS bytes
+ * (as seems to be the case for multiple VIA chipsets).
+ *
+ * It's very chipset-specific if and how the upper 128 bytes are enabled at
+ * all, but this work should be done in coreboot anyway. Libpayload assumes
+ * that coreboot has properly enabled access to the upper 128 bytes and
+ * doesn't try to do this on its own.
+ */
+#define RTC_PORT_STANDARD      0x70
+#ifdef CONFIG_RTC_PORT_EXTENDED_VIA
+#define RTC_PORT_EXTENDED      0x74
+#else
+#define RTC_PORT_EXTENDED      0x72
+#endif
 
 /**
  * Read a byte from the specified NVRAM address.
@@ -52,8 +74,10 @@
  */
 u8 nvram_read(u8 addr)
 {
-	outb(addr, RTC_PORT);
-	return inb(RTC_PORT + 1);
+	u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED;
+
+	outb(addr, rtc_port);
+	return inb(rtc_port + 1);
 }
 
 /**
@@ -64,6 +88,8 @@ u8 nvram_read(u8 addr)
  */
 void nvram_write(u8 val, u8 addr)
 {
-	outb(addr, RTC_PORT);
-	outb(val, RTC_PORT + 1);
+	u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED;
+
+	outb(addr, rtc_port);
+	outb(val, rtc_port + 1);
 }