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| author | Curtis Chen <curtis.chen@intel.com> | 2021-11-19 11:38:12 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 19:43:00 +0000 |
| commit | 0c54461cf99010d9ebeae869f0a486b0268ec860 (patch) | |
| tree | 3b9cf3886eb4fda8a5301f729d24c3649f10ccc1 /payloads | |
| parent | d560ad6e7a372c4e3d1c14d158ca9318c5b1ba90 (diff) | |
soc/intel/alderlake: Add ADLP 4+4+2 power configurations
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).
BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'payloads')
0 files changed, 0 insertions, 0 deletions