diff options
author | John Zhao <john.zhao@intel.com> | 2021-01-06 20:52:16 -0800 |
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committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-01-08 22:01:26 +0000 |
commit | 9c1a335fbcbadb01a89c1dc59dae6094e0d13bc0 (patch) | |
tree | 3b72556a2fbd96d631c06a8f2d244b290bba6c66 /payloads/libpayload/include/storage | |
parent | e862a004d7b6716df44556a23bf7ed9339e1ac6b (diff) |
mb/google/volteer: Configure Delbin USB2 ports for Type C
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/include/storage')
0 files changed, 0 insertions, 0 deletions