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authorArthur Heymans <arthur@aheymans.xyz>2022-05-09 14:33:15 +0200
committerArthur Heymans <arthur@aheymans.xyz>2022-05-16 06:53:46 +0000
commit08769c6d1404c1be0333273d8b988544750ce87d (patch)
treeef37aeb920efea81b84ecf50c2ab990c09541b30 /payloads/libpayload/include/pci
parent159520ed7881d1be2fdd02ee13040e8e21a9833c (diff)
soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'payloads/libpayload/include/pci')
0 files changed, 0 insertions, 0 deletions