intel/tigerlake: Add Acoustic features

On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.

BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions