diff options
author | Furquan Shaikh <furquan@google.com> | 2014-08-24 22:47:20 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-19 23:24:16 +0100 |
commit | ba87e6cc94f039abeabdf2d9d55eebcf23d77823 (patch) | |
tree | 5297e354aa274c686e755587ed2ddda056ddf51f /payloads/libpayload/include/arm64/arch/cache.h | |
parent | c88cca1c38bb2752a7284590ec70a55caf3e490d (diff) |
libpayload: Add support for memory barriers
Add support for memory barriers in arch {arm,arm64,x86}. This is required to
force strict CPU ordering. Definitions are based on FREEBSD atomic.h
definitions.
BUG=chrome-os-partner:31533
BRANCH=None
TEST=Memory barriers tested with ehci driver on arm64
Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552
Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213916
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/include/arm64/arch/cache.h')
-rw-r--r-- | payloads/libpayload/include/arm64/arch/cache.h | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index 2d3175e871..f03d09b9f9 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -70,24 +70,16 @@ /* * Sync primitives */ - /* data memory barrier */ -static inline void dmb(void) -{ - asm volatile ("dmb sy" : : : "memory"); -} - +#define dmb_opt(opt) asm volatile ("dmb " #opt : : : "memory") /* data sync barrier */ -static inline void dsb(void) -{ - asm volatile ("dsb sy" : : : "memory"); -} - +#define dsb_opt(opt) asm volatile ("dsb " #opt : : : "memory") /* instruction sync barrier */ -static inline void isb(void) -{ - asm volatile ("isb" : : : "memory"); -} +#define isb_opt(opt) asm volatile ("isb " #opt : : : "memory") + +#define dmb() dmb_opt(sy) +#define dsb() dsb_opt(sy) +#define isb() isb_opt() /* * Low-level TLB maintenance operations |