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authorDaisuke Nojiri <dnojiri@chromium.org>2014-03-05 15:46:28 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-12-09 18:39:34 +0100
commit0341169761790411208a6644b417f4ae7d1bd88a (patch)
tree678c3b0d57d704b00fab3b769e6d423c626a9a6d /payloads/libpayload/include/arm/arch
parent97345dbc6c2f031158f249b3dda89200784b86b4 (diff)
ARM: API to Map Physical Address to Wipe Memory above 4GB
TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some chars, then verified they can be read from the pointer returned. BUG=chrome-os-partner:25587 BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88 Original-Reviewed-on: https://chromium-review.googlesource.com/188894 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529 Reviewed-on: http://review.coreboot.org/7658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/libpayload/include/arm/arch')
-rw-r--r--payloads/libpayload/include/arm/arch/cache.h9
-rw-r--r--payloads/libpayload/include/arm/arch/virtual.h5
2 files changed, 14 insertions, 0 deletions
diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h
index 470eb55108..647ec42ca2 100644
--- a/payloads/libpayload/include/arm/arch/cache.h
+++ b/payloads/libpayload/include/arm/arch/cache.h
@@ -117,6 +117,15 @@ static inline void write_ttbr0(uint32_t val)
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
}
+/* read translation table base register 0 (TTBR0) */
+static inline uint64_t read_ttbr0(void)
+{
+ uint32_t low, high;
+ asm volatile ("mrrc p15, 0, %[low], %[high], c2" :
+ [low] "=r" (low), [high] "=r" (high));
+ return ((uint64_t)high << 32) | low;
+}
+
/* read translation table base control register (TTBCR) */
static inline uint32_t read_ttbcr(void)
{
diff --git a/payloads/libpayload/include/arm/arch/virtual.h b/payloads/libpayload/include/arm/arch/virtual.h
index 328c3aa34e..e51530d252 100644
--- a/payloads/libpayload/include/arm/arch/virtual.h
+++ b/payloads/libpayload/include/arm/arch/virtual.h
@@ -30,6 +30,8 @@
#ifndef _ARCH_VIRTUAL_H
#define _ARCH_VIRTUAL_H
+#include <arch/cache.h>
+
extern unsigned long virtual_offset;
#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset)
@@ -38,4 +40,7 @@ extern unsigned long virtual_offset;
#define virt_to_bus(addr) virt_to_phys(addr)
#define bus_to_virt(addr) phys_to_virt(addr)
+void *lpae_map_phys_addr(unsigned long pa_mb, enum dcache_policy policy);
+void lpae_restore_map(void);
+
#endif