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authorRaihow Shi <raihow_shi@wistron.corp-partner.google.com>2022-07-14 16:26:07 +0800
committerMartin L Roth <gaumless@tutanota.com>2022-07-19 01:49:41 +0000
commit44bc4cd5d40db8be7796f1bc52bdab3325941e9b (patch)
tree85f460a3e1be5e42e77c1d66543a96599101dd49 /payloads/libpayload/arch/arm64/main.c
parent50eef6566b223eb2a6c027e9a862bc279bd06ed7 (diff)
mb/google/brask/variants/moli: correct USB3 port2 tx_de_emp
Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX failed. BUG=b:236661824 TEST=emerge-brask coreboot and check USB3 port2 RX pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm64/main.c')
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