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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-13 14:50:38 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-11-23 17:50:55 +0000 |
| commit | f9b6f2d3558903ec8a0fec055d363ac6fb24c0df (patch) | |
| tree | 7d944935cdc1acf6e9722a10097f3afb814b1069 /payloads/coreinfo/cpuid.S | |
| parent | 62f788e24469c0e12dbf427594cc8150ffa4336f (diff) | |
arch/riscv/romstage: Start from assembly
Without this it would use the exception handler from the previous
stage.
Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68840
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/coreinfo/cpuid.S')
0 files changed, 0 insertions, 0 deletions