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authorNick Vaccaro <nvaccaro@google.com>2021-02-16 19:06:16 -0800
committerNick Vaccaro <nvaccaro@google.com>2021-03-05 04:28:36 +0000
commit2f78ce0995a6dd0630802a918438c4d3b1c328fc (patch)
treed4fce211c6f5e4f34daf0bbe7c5de58468d74fc5 /payloads/coreinfo/cpuid.S
parent29144554fb1e258f5a6bce86c5c2d75620039dd2 (diff)
mb/google/volteer: Fix FPMCU pwr/rst gpio handling
1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'payloads/coreinfo/cpuid.S')
0 files changed, 0 insertions, 0 deletions