nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage

Enabling sync flood on DRAM MCE directly after ECC clear can
lead to a system hang with no way to determine the offending
DRAM module.  Clear MCEs after ECC setup, but do not enable
sync flood until NB setup in ramstage to allow time for any
MCEs to accumulate in the status registers.  Before enabling
sync flood on MCE, determine if any MCEs were logged during
ramstage execution and display them on the serial console.

Also clear the DRAM ECC sync flood bits during DRAM training
and initial ramstage execution.

Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14192
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions