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authorFelix Held <felix.held@amd.corp-partner.google.com>2021-09-30 20:46:15 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-10-11 15:16:16 +0000
commitc3a9e5371453c9ce713ce6625105bde66ff28d76 (patch)
tree2a2359064778d161cafde20132631701ed80d7d0 /gnat.adc
parent0cd81c325c631108db255546229a95ec2c4fd82b (diff)
mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'gnat.adc')
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