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authorAngel Pons <th3fanbus@gmail.com>2020-07-22 17:30:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:31:22 +0000
commit93d9517795b58fca2639bc66e359a61219e82b81 (patch)
tree2562d8496997da412d14cd1ab807965a2eb3389c /gnat.adc
parent67573371d5ade1ad388316585901ee9d0edfe512 (diff)
nb/intel/ironlake: Add definition for QPI Link PCI device
On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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