mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
         reset on JSLRVP.

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

0 files changed, 0 insertions, 0 deletions