diff options
| author | ZhengShunQian <zhengsq@rock-chips.com> | 2015-03-06 14:45:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:28:22 +0200 |
| commit | 82a7bc45f77a8223fc3072e8c76de80685767186 (patch) | |
| tree | 9e039ac59e6d877df0ceb0b0312362adf8464685 /documentation/RFC/chip.tex | |
| parent | 823f6072a7dfa59e3048c2db175e61caabf63cb3 (diff) | |
veyron: add new SDRAM configuration with ram-code 1101b
This add hynix-2GB SDRAM(H5TC4G63AFR-PBA), whose timing is the same as
H5TC4G63CFR-PBA, to veyron boards.
BUG=None
BRANCH=veyron
TEST=build on mighty and boot on mighty board with ram-id reworked
Change-Id: I3ae5e65e60e18414cf4de6fbcc5bed736b1492de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b22029f9b05ebb9a775266a7e3aae38b50c1883a
Original-Change-Id: If17fb002f2816990e1706833b37ac6be345e540b
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256307
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/9848
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'documentation/RFC/chip.tex')
0 files changed, 0 insertions, 0 deletions