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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-08 23:41:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-11 07:32:17 +0000 |
| commit | 0cdcdc736ea28be7bfc6eabdac2430ecf6ee409c (patch) | |
| tree | 5664b5a7f0b3712ba843892cd4f05e58f1ab48f8 /configs/config.pcengines_apu1 | |
| parent | dea42e011a126c4fdc9ab62f6d6c449df4740f82 (diff) | |
soc/intel/elkhartlake: Update FSP-S FuSa related settings
Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.pcengines_apu1')
0 files changed, 0 insertions, 0 deletions