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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-04-28 23:34:14 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 18:01:06 +0000 |
| commit | dddaeed4c142a23b05e68b1af77026bf7f2676e9 (patch) | |
| tree | 4f41293023bce8f72c27512cae23212429522d42 /configs/config.ocp_tiogapass | |
| parent | 8e3787eaf01f84b449cca3d37ec584ad77228b86 (diff) | |
soc/intel/alderlake: Update cpu and pch tracehub modes
The patch gets the cpu and pch's tracehub mode from the debug area
of the Descriptor Region and updates the respective UPDs.
TEST=Build, verify the tracehub mode values.
Update CPU' and PCH's Trace Hub modes:
img=coreboot.rom
printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc
printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc
Check coreboot logs:
[DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Diffstat (limited to 'configs/config.ocp_tiogapass')
0 files changed, 0 insertions, 0 deletions