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author | Yu-Ping Wu <yupingso@chromium.org> | 2024-07-17 10:39:48 +0800 |
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committer | Yu-Ping Wu <yupingso@google.com> | 2024-07-19 00:40:21 +0000 |
commit | c0540a3fc2d79328708f34204dbf02df443d9fb8 (patch) | |
tree | 0241b9574ea901e5ae959efefbb5c7748160c36b /configs/config.ocp_tiogapass | |
parent | 1b19d292db79eafc78ad522d43ca44cd3295655c (diff) |
security/vboot: Introduce vbnv_platform_init_cmos()
Most x86 platforms use CMOS as the vboot nvdata (VBNV) backend storage.
On some platforms such as AMD, certain CMOS registers must be configured
before accessing the CMOS RAM which contains VBNV. More precisely,
according to AMD's spec [1], the bit 4 of Register A of CMOS is bank
selection. Since VBNV is accessed via bank 0 (see the MC146818 driver),
the bit must be cleared before the VBNV can be successfully written to
CMOS. Saving VBNV to CMOS may fail in verstage, if CMOS has lost power.
In that case, all the CMOS registers would contain garbage data.
Therefore, for AMD platforms the bit must be cleared in verstage, prior
to the first save_vbnv_cmos() call.
Introduce vbnv_platform_init_cmos(), which is no-op by default, and can
be defined per platform. The function will be called from vbnv_init() if
VBOOT_VBNV_CMOS.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: Ic899a827bd6bb8ab1473f8c6c03b9fde96ea6823
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83494
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.ocp_tiogapass')
0 files changed, 0 insertions, 0 deletions