summaryrefslogtreecommitdiff
path: root/configs/config.ocp_tiogapass
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2021-03-22 20:10:31 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-03-26 04:53:36 +0000
commit7d85d43f18d9607a7d41eb401f8d096e28d98c18 (patch)
tree95f47b843fbbd7d3f44f45d11460c50db42741bd /configs/config.ocp_tiogapass
parentefe858b1706568fcfefe4d582cebbb32de9cd596 (diff)
mb/google/brya: Update ddr config
Fixed ddr config to override the FSP default value. BUG=b:182772421 TEST=Built image and passed memory training. Without this change: RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 } With this change: RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 } Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'configs/config.ocp_tiogapass')
0 files changed, 0 insertions, 0 deletions