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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-24 13:48:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-30 08:07:26 +0000 |
| commit | 092813a50ce4198d622daa809181216b6ffd1bd4 (patch) | |
| tree | d32b59c3177e66590382bc517aa31f3e0d4ca062 /configs/config.asus_p2b_ramdebug | |
| parent | 2821cb498b6d85548e42852b6e1ad25cb648c44d (diff) | |
soc/intel/alderlake: Add initial chipset.cb
Similar to the chipset.cb for TGL, this patch gives alias names to all
of the published PCI devices.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.asus_p2b_ramdebug')
0 files changed, 0 insertions, 0 deletions