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authorSubrata Banik <subrata.banik@intel.com>2021-10-27 23:04:07 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-10-30 18:45:09 +0000
commit6cdc838b0d39398ff7662e425ed330fdc1e3333c (patch)
treef3a13823fffe374c0f263a8702726135252d5f06 /Makefile
parent3afa467a880392f4dbbbc69373eb555731e738b4 (diff)
soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table
Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type table. Change-Id: I1ec442cf0bd830db99e3636445724b6be01c5564 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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