mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl

Configure GPIO pins, add Kconfig options and enable
TPM device in devicetree.

Add H1 TPM IRQ GPIO pin in gpio.c

BUG=none
BRANCH=firmware-brya-14505.B
Cq-Depend: chromium:3774914
TEST=Boot the image and check the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>

0 files changed, 0 insertions, 0 deletions