soc/amd/picasso: Update southbridge

Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary.  The most notable changes are:
 * Update the index values for the C00/C01 interrupt routing
 * FORCE_STPCLK_RETRY is not present
 * PCIB is not defined
 * FCH MISC Registers 0xfed80e00 numbering has changed
 * C-state base moves from PM register to MSR
 * Add option to determine the intended MUX settion for LPC vs. eMMC
 * Remove the LEGACY_FREE option

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions