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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-20 16:28:33 -0600
committerMartin Roth <martinroth@google.com>2019-10-20 16:31:54 +0000
commit39a4ac1502b658d4ef6b57c50a0e386eff91364a (patch)
tree6c8fcc4f674d179a98eb5c8f9264d1446e8740e8 /Makefile.inc
parent06fd982030a9ec74c38a6a075e243ff9a931e0ed (diff)
soc/amd/picasso: Update southbridge
Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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