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authorXiang Wang <wxjstz@126.com>2018-08-09 16:20:35 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-10 15:03:58 +0000
commitcda59b56ba1af83a64579901a5395c1b3c1bf519 (patch)
tree1ea1d63305663f76623b8db878e33f72b4867f82 /MAINTAINERS
parentaa5f821ee3313b869784eec25fab5da265225738 (diff)
riscv: update misaligned memory access exception handling
Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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