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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-09-20 23:52:43 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-26 15:36:40 +0000
commitce8763fb138afe8261301fc6a3638b7b18b381ac (patch)
tree2e42aee31faa00fb0dbdc3d13d03b1f63a7f3757 /MAINTAINERS
parent534b564345af4f6111f7717f9c7f7286599d1bf7 (diff)
mb/lowrisc: Remove the Nexys4DDR port
This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'MAINTAINERS')
-rw-r--r--MAINTAINERS2
1 files changed, 0 insertions, 2 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index ca8a6f2a74..4d27129c0a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -124,10 +124,8 @@ M: Ronald Minnich <rminnich@gmail.com>
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
S: Maintained
F: src/arch/riscv/
-F: src/soc/lowrisc
F: src/soc/ucb/
F: src/mainboard/emulation/*-riscv/
-F: src/mainboard/lowrisc
POWER8 ARCHITECTURE
M: Ronald Minnich <rminnich@gmail.com>