From ce8763fb138afe8261301fc6a3638b7b18b381ac Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Thu, 20 Sep 2018 23:52:43 +0200
Subject: mb/lowrisc: Remove the Nexys4DDR port
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.

Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.

Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 MAINTAINERS | 2 --
 1 file changed, 2 deletions(-)

(limited to 'MAINTAINERS')

diff --git a/MAINTAINERS b/MAINTAINERS
index ca8a6f2a74..4d27129c0a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -124,10 +124,8 @@ M:	Ronald Minnich <rminnich@gmail.com>
 M:	Jonathan Neuschäfer <j.neuschaefer@gmx.net>
 S:	Maintained
 F:	src/arch/riscv/
-F:	src/soc/lowrisc
 F:	src/soc/ucb/
 F:	src/mainboard/emulation/*-riscv/
-F:	src/mainboard/lowrisc
 
 POWER8 ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>
-- 
cgit v1.2.3